1. Field of the Invention
The present invention relates to a structure of an electric circuit, more specifically, in a circuit where synchronization is necessary, to a technique for reducing the variation of shift (delay) with a synchronization signal occurring from the variation of the transistor characteristic.
2. Description of the Related Art
Generally an electric circuit which synchronizes by taking in data corresponding to a common signal and preparing calculation results is used, using the common signal such as a clock.
Note that, in an electric circuit, when the structure of the electric circuit is complicated, the operation of the entire electric circuit has to be executed at a certain rhythm, otherwise a shift occurs in the operation timing due to the difference of the processing period of times of each part, thus not operating satisfactorily. Therefore, in order to synchronize the entire electric circuit, a basic pulse is supplied commonly to the electric circuit. In this specification, the basic pulse is referred to as a common signal or a synchronizing signal. Typically there are as the common signal, a clock signal, a clock back signal, a trigger signal and the like. Note that, the clock back signal is a signal which is an opposite phase to a clock signal.
Note that, in this specification; a trigger signal refers to a signal which triggers a change in state. More specifically, an electric circuit such as a multivibrator does not have an ability to continue oscillation by itself. However, if an input pulse is input from the outside, an output pulse with a time width differing from that of the input pulse is output. Since such an input pulse has a trigger function to oscillate the output pulse, it is referred to as the trigger signal.
In the electric circuit, conventionally a common signal is input to the controlling electrode (gate terminal) of the transistor, and a signal synchronized with the common signal is fowled by making use of the change in resistance between the input terminal and the output terminal of the transistor.
Note that, in this specification, the input terminal and the output terminal of the transistor refer to a source region and a drain region of the transistor. Namely, one of the source region and the drain region of the transistor is the input terminal, and the other is the output terminal.
However, there is a variation in the transistor characteristic, and due to this variation, a variation occurred in the signal which is to synchronize with the common signal.
As a method of structuring the electric circuit, there is known a method of using a CMOS by structuring a logic circuit combining an n-channel MOS transistor and a p-channel MOS transistor.
In a MOS transistor used in the CMOS, when a control electrode (gate terminal) voltage is at a threshold voltage or lower, a current hardly flows, and when it exceeds a threshold voltage, the current starts to increase. Therefore, the variation of the threshold voltage is a problem in that variation occurs in a signal which is to synchronize with the common signal.
As a specific example of the structure of the conventional electric circuit, FIG. 3 shows a circuit using an AND. The AND has two input terminals, and when there is an input of Hi to the two input terminals (when there is an input of the same voltage as the higher power source voltage), there is an output of Hi. A common signal is input to one of the two input terminals of the AND, and a control signal is input to the other.
Note that, in this specification, the control signal refers to a video signal, a start pulse or the like.
FIG. 4 shows an example of a circuit when the AND in FIG. 3 is structured by CMOS. Reference numerals 101, 102 and 103 indicate p-channel MOS transistors, and reference numerals 104, 105 and 106 indicate n-channel MOS transistors. Here, Vdd and Vss are power source supply lines, and Vdd>Vss is satisfied.
The electric circuit shown in FIG. 3 is input with a common signal, a control signal 1 and a control signal 2 shown in FIG. 5. Ideally, as shown in FIG. 5, it is preferable that output 1 is output only for the time the common signal and the control signal 1 are simultaneously Hi, and output 2 and output 3 are output only for the time the common signal and the control signal 2 are simultaneously Hi. In this way, a signal synchronized with the common signal may be formed.
In actuality, by passing the AND, signals such as the common signal and the control signal are delayed. If all the transistors have totally the same characteristics, the same delay occurs in all the AND. However, all the transistors do not have the same characteristics, and therefore delays and also variations occur (FIG. 7). Further, although not shown here, variations occur in the waveform such as the rise time and the fall time of the output signal.
FIG. 6 shows an example where variation occurs in the threshold voltage of the MOS transistor. Here, the axis of abscissa Vg indicates the voltage applied to the gate terminal, and the axis of ordinate log (Id) indicates the current flowing between the source region and the drain region of the transistor in a log display. If a constant voltage is applied between the source region and the drain region of the transistor, while a current flowing between the source region and the drain region is measured and the voltage applied to the gate terminal is changed, a current starts to flow from a certain voltage (threshold voltage).
By variation of the transistor characteristics due to the variation of the threshold voltage, variation of propagation delay and variation of waveform as shown in FIG. 7 may occur, and a variation occurs in the signal which is to synchronize with the clock.
The characteristics of the plurality of transistors of the electric circuit, differ respectively, and thus there is a variation in a threshold voltage of the plurality of transistors.